In accordance with the prior art, it is well known that ESD is a main factor to cause electronic devices or systems to be damaged by electrical overstress (EOS). ESD may make semiconductor devices and computer systems be damaged permanently, hence it can influence functions of integrated circuits (IC) and make the electronic devices operate abnormally. In most situations, ESD is induced artificially, but it is still hard to avoid this effect. The reason is that the static electricity would accumulate in human bodies, instruments and store equipments during the processes of manufacturing, producing, assembling, storing or moving of the electronic devices and systems. Even the electronic devices would accumulate static electricity itself. In some circumstances, due to contacting the electronic devices with human bodies, instruments and store equipments unknowingly, it may form a path of ESD and make the electronic devices or systems be damaged unexpectedly.
In order to prevent the electronic devices from being damaged by the ESD current effectively, the ESD protection circuits used to drain the ESD current away become necessary. Up to now, a lot of technology about used components or manufacturing improvement of the components in the ESD protection circuits has been accumulated for successor' reference. In general, the components of the ESD protection circuits may include reverse-biased diode, bipolar transistor, MOS component and silicon-controlled rectifier (SCR), etc. In these ESD protection circuits, most of them use the components that can operate at first breakdown region to drain out the ESD current. In the first breakdown region, the component of the ESD protection circuits wouldn't be damaged. However, there is still a limit. It is so-called secondary breakdown region. When the components operate at the second breakdown region due to the additional EOS current or voltage, they will be damaged permanently. Further, these components can also be turned on, such as turning on a FET component to form a current grounding path between its source and drain, to make the ESD current be passed to the ground via the current grounding path.
In general, the ESD protection circuits are designed according to the human body model (HBM) and machine model (MM). However, as the deep sub-micron techniques became the main stream of the market, the ESD of the charge device model (CDM) can cause the damage of gate oxide very easily when the thickness of the gate oxide is only 50A made by 0.25 micro manufacturing processes.
The so-called HBM or MM indicates that the static electricity of external human bodies or machines is passed to internal circuits via pins of IC. Hence, the ESD protection circuits are usually disposed beside the input or output boding pad of the internal circuits directly to drain off the ESD current. On the other hand, the static charges are stored in the substrate of electronic components, when a pin is grounded, these charges will be discharged via the grounded pin. The ESD of CDM can make the gate of input end be punched through very easily. Even if the ESD protection circuit is already applied to the gate of the input end, in most situations, it still cannot be turned on timely to drain off the immediately generated ESD current of CDM.
Please refer to FIG. 1, which is a schematic diagram of a conventional ESD protection circuit. The ESD protection circuit 10 includes a primary ESD clamp circuit 12, secondary ESD clamp circuit 14 and resistor 16. The resistor 16 first connects with the secondary ESD clamp circuit 14 in series and then connects with the primary ESD clamp circuit 12 in parallel. The ESD protection circuit 10 is disposed beside the input boding pad 19 to prevent the internal circuit 21 from the influence due to the ESD current 25 induced by the external ESD voltage 23 damages the complementary MOS transistors 18.
When ESD of HBM or MM is induced at the input boding pad 19, the external ESD voltage 23 would bias the gates of the complementary MOS transistors 18. Hence, the main function of the secondary ESD clamp circuit 14 is to resist the exceeding ESD voltage 23 so as to prevent the complementary MOS transistors 18 from being damaged by the ESD voltage 23. In general, the secondary ESD clamp circuit 14 is carried out by employing a short-channel NMOS component, which can't bear high ESD voltage 23. Hence, the resistor 16 and the primary ESD clamp circuit 12 should be added to prevent the exceeding ESD current 25 from passing the secondary ESD clamp circuit 14 composed of the NMOS component. The ESD current 25 is mainly drained off by the primary ESD clamp circuit 12, hence the primary ESD clamp circuit 12 should be composed of the components that can bear large current. These components have high turn-on voltage and slow turn-on speed generally, hence the primary ESD clamp circuit 12 should cooperate with the secondary ESD clamp circuit 14 for effectively protecting the gates of the complementary MOS transistors 18. However, the ESD protection circuit 10 is equivalent to a combination of large resistors and capacitors. It has large RC delay time for the input signal and is not suitable for applications with high-frequency signals or current input signals.
Please refer to FIG. 2, which is a schematic diagram of another conventional ESD protection circuit. In order to improve the shortcoming of the ESD protection circuit 10 in the applications with high-frequency signals or current input signals, the ESD protection circuit 50 only employs the NMOS transistor 51 for resisting the ESD effect without additional ESD clamp circuit and shout resistor. Hence, the equivalent input resistor of the input end is decreased so that the ESD protection circuit 50 is more suitable than the ESD protection circuit 10 shown in FIG. 1 for the applications with high-frequency signals or current input signals. However, the ESD protection circuit 50 is composed of the NMOS transistor 51, whose gate is grounded, without the shout resistor 16 shown in FIG. 1. Its robustness is avoidably challenged by the ESD current passed through the NMOS transistor 51. When the ESD voltage 54 is induced, the ESD current 58 is first passed to the ESD protection circuit 50 via the input boding pad 56 so that the analog circuit 52 will not be damaged directly.
However, as the advanced manufacturing processes, such as light doped drain (LDD) and silicided diffusion processes, are employed, the compact degree of integrated circuits (IC) and the calculation speed are increased, but the ESD resisting ability of the IC (including the internal circuits and ESD protection circuits) is decreased.
In order to overcome the problem regarding the decreasing of the ESD resisting ability of the LDD structure, the ESD-implant process is developed. Its method is to make two different kinds of NMOS components in a complementary MOS (CMOS) manufacturing process; one is of the LDD structure used for the internal circuit with the and the other isn't of the LDD structure used for the input/output stage. In order to make these two kinds of components together in the manufacturing process at a time, an additional ESD-implant mask and some additional processing steps are necessary in the original process. Furthermore, due to the NMOS components made by the ESD-implant process is different from the NMOS components with the LDD structure, it needs some additional processes and design to obtain their SPICE parameters to facilitate the simulation and design of circuits.
As per the silicided diffusion process, its main objective is to reduce the stray resistances of the drain and source of the MOS component to increase the operation speed of the MOS component for high-frequency applications. Since the stray resistances are very small, as the ESD occurs, the ESD current is easily passed to the LDD structure of the MOS components to damage them. Even if the MOS component with large width/length (W/L) ratio is used as output stage, the ESD resisting ability still can't be improved. In order to increase the ESD resisting ability of the output stage the silicided diffusion blocking process is developed. It removes part of the silicide layer of the output-stage MOS component to make the source and drain resistances of the MOS increased to improve the ESD resisting ability of the MOS component.
Please refer to FIGS. 3a and 3b, which are schematic diagrams of MOS components without and with a silicide block, respectively, according to the prior art. In order to dispose the silicide block, the spacing between the drain and source should be large enough. Although the silicide block is used to increase the resistance between the drain and the poly gate to restrict the electric current and hence improve the ESD resisting ability of this kind of MOS component, it increases the occupying area of the MOS due to the increase of the spacing between the source and drain. Hence, the number of the MOS components able to be made in a single wafer would be influenced. Further, in the viewpoint of input end, the increase of resistance would increase the RC delay time of the input signal. Hence, this kind of components is not suitable for the inputs with high-frequency signal or current signals.
Please refer to FIG. 4, which is a schematic diagram of an ESD protection circuit disclosed in U.S. 2002/0130390. Both of the ESD protection circuit 100 and the internal circuit 102 are at least connected with two power lines 103 and 104. Therein, the power lines 103 and 104 are preferable to be a power supply line and ground line, respectively.
The ESD protection circuit 100 includes an ESD restricting circuit 110 disposed between the power lines 103 and 104, which is composed of a CMOS inverter 112 and a RC retarder 113. It can make the ESD current induced by the ESD voltage obtain an ESD path formed by a forward-biased diode pair (D1, 2 or D3, 4) or a substrate-triggered MOS transistor 117 of the ESD restricting circuit 110 disposed between the power lines that is operated at the first breakdown region (or snapback breakdown region). The CMOS inverter 112 is used to trigger the substrate-triggered MOS transistor 117. The gate of the substrate-triggered MOS transistor 117 is connected with the power line 104 via a resistor R2 so that the substrate-triggered MOS transistor 117 is turned off in the situation without ESD. The ESD protection circuit 100 is directly disposed between the input bonding pad 115 and the internal circuit 102 for providing the ESD path. The diodes D1˜4 are equivalent to capacitances Cjn1˜4. They are connected in series so that the total equivalent capacitance is decreased as the number of the diodes increases.
In the ESD protection circuit 100 shown in FIG. 4, all of the MOS components in the substrate-triggered MOS transistor 117, CMOS inverter 112 and RC retarder 113 (the capacitor C is carried out by employing a MOS component) has the silicide blocks disposed in their drains as mentioned above. With the silicide blocks, the ESD resisting ability can be improved certainly, but the increased equivalent input resistance would restrict the application of this kind of component in high-frequency field. Further, the occupying area of this kind of MOS components is larger that of the MOS components with silicide block. Hence, the number of the MOS components able to be made in a single wafer would be decreased.
Accordingly, as discussed above, the conventional ESD protection circuit still has some drawbacks that could be improved. The present invention aims to resolve the drawbacks in the prior art.